Structure and process for making substrate packages for high frequency application

ABSTRACT

A process for fabricating a microelectronic structure. The process comprises processing a metal carrier having a top surface and a bottom surface, wherein the top surface and the bottom surface are processed to promote adhesion, forming a dielectric layer around the metal carrier, wherein the dielectric layer substantially covers the top surface and the bottom surface of the metal carrier, and applying a first patterned layer of conductive material to the microelectronic structure. In one preferred embodiment, the process further comprises comprising sintering the metal carrier, the dielectric layer, and the first patterned layer of conductive material. In one preferred embodiment, the process further comprises forming a via hole through the metal carrier before the forming of the dielectric layer around the metal carrier, wherein the forming of the dielectric layer comprises forming the dielectric layer inside the via hole.

BACKGROUND OF THE INVENTION

The present invention relates generally to packaging for integratedcircuits. More particularly, the present invention relates to astructure and process for manufacturing substrate packages for highfrequency application.

As substrate packages for integrated circuits on semiconductor chipsbecome denser and faster, there has been a significant increase in therequirements that the substrate packages need to meet. For example thesubstrate packages designed for microwave applications involve highpower density chips and interconnections requiring high currents. Thisimposes severe restrictions in terms of thermal management and alsocurrent carrying capability, on these substrate packages. The substratepackages aimed at applications especially in communications need to bethin and highly brazable. Also, certain electrical design requirementsdictate that the backside of the substrate packages be metallized forproviding a ground cage and slot line type transmission lines byembedding large area metal features in the dielectric layer. Thesubstrate packages for digital applications require denser wiring andfiner features (lines and via holes) to be incorporated at lower costs.It is advantageous if these substrate packages would be available invarious coefficient of thermal expansions ranging from 3×10⁻⁶ to18×10⁻⁶C⁻¹ expanding their application space. There is also a strongdrive to reduce the defect density in both the chip carriers and in thepassive components in the substrate packages.

The conventional method to build such substrate packages (SCM's andMCM's) utilizes multi-layer-ceramic (MLC) processing. This involvesmaking green sheets from the dielectric powder of choice, screeningthose green sheets with paste(s) of selected metallization to producepatterns and through sheet connections, or vias, stacking these screenedgreen sheets, laminating the green sheets, and then sintering the greensheets to form a three-dimensionally connected substrate package.Sintering large size substrate packages with the very high metalloading, typically required for the communications packages, createsconsiderable difficulties in controlling the shrinkage, distortion andflatness of substrate packages at the end of the process. Specialprocessing steps have to be added to assure the flatness of thesubstrate packages. Also, the backside metallization required to buildconventional substrate packages is done by a combination of physicaldeposition methods and electroplating. The high tolerance required forfabricating substrate packages with very fine features cannot beincreased beyond a certain limit due to the distortion of green sheetsduring various processing steps. Overall processing costs of thesubstrate packages produced using MLC techniques are relatively higherbecause of the longer cycle times. Therefore there is a need to developcost effective ways to produce such substrate packages.

BRIEF SUMMARY OF THE INVENTION

An aspect of the present invention is a process for fabricating amicroelectronic structure. The process comprises processing a metalcarrier having a top surface and a bottom surface, wherein the topsurface and the bottom surface are processed to promote; adhesion,forming a dielectric layer around the metal carrier, wherein thedielectric layer substantially covers the top surface and the bottomsurface of the metal carrier, and applying a first patterned layer ofconductive material to the microelectronic structure. In one preferredembodiment, the process further comprises sintering the metal carrier,the dielectric layer, and the first patterned layer of conductivematerial. In one preferred embodiment, the process further comprisesforming a via hole through the metal carrier before the forming of thedielectric layer around the metal carrier, wherein the forming of thedielectric layer comprises forming the dielectric layer inside the viahole.

Another aspect of the present invention is a microelectronic structurecomprising a metal carrier having a top surface and a bottom surface, adielectric layer formed around the metal carrier, the dielectric layersubstantially covering the top surface and the bottom surface of themetal carrier, and a first patterned layer of conductive materialoverlying the dielectric layer. In one preferred embodiment, the firstpattern layer of conductive material overlies the metal carrier. Theseand other aspects of the invention will become apparent upon a review ofthe following detailed description of the presently preferredembodiments of the invention, when viewed in conjunction with theappended drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates, in cross-section, a portion of a substrate package,in accordance with one preferred embodiment of the invention;

FIGS. 2-5 illustrate, in cross-section, process steps for thefabrication of a strate package, in accordance with one preferredembodiment of the invention;

FIG. 6 illustrates, in cross-section, a portion of a first substratepackage connected to a portion of a second substrate package and aportion of a third substrate package, in accordance with one preferredembodiment of the invention; and

FIG. 7 illustrates, in cross-section, a portion of a substrate package,in accordance with one preferred embodiment of the invention.

It should be appreciated that for simplicity and clarity ofillustration, elements shown in the Figures have not necessarily beendrawn to scale. For example, the dimensions of some of the elements areexaggerated relative to each other for clarity. Further, whereconsidered appropriate, reference numerals have been repeated among theFigures to indicate corresponding elements.

DETAILED DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS OF THEINVENTION

Shown in FIG. 6, in cross-section, is substrate package 20 comprisingmultiple microelectronic structures 21, such as first microelectronicstructure 24, second microelectronic structure 26, third microelectronicstructure 28) and semiconductor chip 22. Please note that FIG. 6illustrates only a portion of substrate package 20. For the sake ofclarity, the entire substrate package 20 has been left out of FIG. 6.

The structure and process used to fabricate substrate package 20 of thepresent invention provides a means to manufacture a low costmicroelectronic structure 21 using a combination of metal carrier 30with ceramics and polymers. The structure and process of the presentinvention allow one to fabricate microelectronic structures 21 with finelines, spaces and via holes between layers, control the overallcoefficient of thermal expansion of the microelectronic structures 21,and form a multitude of microelectronic structures 21 including chipcarriers, capacitors, chip carriers with integral capacitors or otherpassive components as a portion of the chip carrier. The structure andprocess of the present invention also allows one to fabricate multiplemicroelectronic structures 21 in parallel and test them before assembly,thereby significantly reducing the defect levels in the final substratepackage 20. The structure of the present invention may comprise one ormore layers of metal carriers 30, dielectric layers 40, and verticalinterconnects to make up a microelectronic structure 21 designed to meetan application where metal carriers 30, dielectric layers 40, andvertical interconnects, in combination, provide the desired coefficientof thermal expansion, mechanical strength, and also the electrical andthermal management performance. There are many possible combinations forsubstrate packages 20 having microelectronic structures 21 built withmetal carrier 30. Only a few representative examples will be describedbelow.

FIGS. 2-4 illustrate a process for fabricating microelectronic structure21 having metal carrier 30. The process comprises processing metalcarrier 30 having top surface 32 and bottom surface 34. Metal carrier 30is formed from any material that permits the flow of electrons.Preferably metal carrier 30 comprises material selected from the groupconsisting of titanium, tantalum, molybdenum, tungsten, nickel, copper,gold, silver and aluminum, however, metal carrier 30 may comprise anyother metal or material that permits the flow of electrons. Metalcarrier 30 conforms to the shape of a generally flat sheet of material,as illustrated in FIG. 2. Top surface 32 and bottom surface 34 of metalcarrier 30 are processed to promote adhesion. Top surface 32 and bottomsurface 34 may be processed to promote adhesion in any one of a numberof ways known to one of ordinary skill in the art, such as, for examplewet etching, plasma etching, ion milling, and reactive ion etching.Other process, such as plasma surface treating following by an optimizedcleaning process, may also be used to process metal carrier 30.Preferably, metal carrier 30 has a thickness of about 0.03 mm to about0.20 mm, and more preferably about 0.05 mm.

In one preferred embodiment, via holes 50 are formed through metalcarrier 30, as illustrated in FIG. 3. Via holes 50 permit the flow ofelectrical signals and allow microelectronic structure 21 to beelectronically connected to another electronic device such as a secondmicroelectronic structure 21 or a semiconductor chip 22. For example,via holes 50 can carry an electrical signal from semiconductor chip 22,to a one microelectronic structure 21, such as first microelectronicstructure 24, or through one microelectronic structure 21 and to anothermicroelectronic structure 21, such as third microelectronic structure28, as illustrated in FIG. 6. Preferably, via holes 50 are formed bypatterning metal carrier 30 using lithography and a wet or dry etchingprocess, however via holes 50 can be formed in any one of a number ofways, such as, for example, using a mechanical punching process, laserassisted wet etching, laser drilling, or any other process or method forforming holes in a metallic structure, such as metal carrier 30, knownto one of ordinary skill in the art. In one preferred embodiment, viaholes 50 are formed through metal carrier 30 before forming dielectriclayer 40 around metal carrier 30. In another preferred embodiment, viaholes 50 are formed through metal carrier 30 after forming dielectriclayer 40 around metal carrier 30.

In another preferred embodiment, via holes 50 are not formed throughmetal carrier 30, as illustrated in FIG. 7. In this embodiment,protective layer 65 is formed around metal carrier 30. Protective layer65 prevents degradation and oxidation of metal carrier 30. Protectivelayer 65 is comprised of material that can prevent a significant amountof oxide from forming on metal carrier 30 and that can protect metalcarrier 30 In one preferred embodiment, protective layer 65 comprises atleast one material selected from the group consisting of nickel, gold,and any other metallic, environmentally stable material known to one ofordinary skill in the art. Protective layer 65 substantially covers allthe surfaces of metal carrier 30 except for top surface 32, asillustrated in FIG. 7. In one preferred embodiment, additionaldielectric layers 40 are placed over metal carrier 30 and protectivelayer 65, as illustrated in FIG. 7. These additional dielectric layers40 have gaps or via holes between them, wherein conductive material 60is placed between the gaps. Preferably, conductive material 60 is placedon only one side of metal carrier 30, as illustrated in FIG. 7, thuscreating a microelectronic structure 21 comprising a ground side 36 thatcan act as a ground plate.

In one preferred embodiment, after metal carrier 30 has been processed,dielectric; layer 40 is formed around metal carrier 30. Dielectric layer40 prevents electrical charge from migrating between metal carrier 30and other structures, such as electrodes 70 or via hole 50. Dielectriclayer 40 is comprised of any material that can prevent a significantamount of electrical charge from migrating between metal carrier 30 andother structures. In one preferred embodiment, dielectric layer 40comprises material selected from the group consisting of alumina,mullite, aluminum nitride, forsterite, glass, ceramic, oxide, and anyother insulating material known to one of ordinary skill in the art.Dielectric layer 40 substantially covers all the surfaces of metalcarrier 30 including top surface 32 and bottom surface 34. In someapplications, it is actually required that dielectric layer 40 coveronly a portion of the surfaces of metal carrier 30. For example, in onepreferred embodiment, dielectric layer 40 is not formed around metalcarrier 30, but rather, dielectric layer 40 is formed around a selectportion of metal carrier 30 and substantially covers only a selectportion of metal carrier 30. In another preferred embodiment, dielectriclayer 40 is formed around metal carrier 30, and a portion of dielectriclayer 40 is later removed.

Dielectric layer 40 may be formed in any one of a number of ways knownto one of ordinary skill in the art, such as, screening a dielectricpaste, casting a polymer sheets, thin film deposition, or growing anoxide layer (oxidation). The flexibility achieved by allowing dielectriclayer 40 to be formed in any one of a number of ways allows one toproduce substrate packages 20 comprising microelectronic structures 21with different functionality by using different fabrication techniques.Microelectronic structures 21 can later be joined together, asillustrated in FIG. 6, to create substrate package 20. In one preferredembodiment, the forming of dielectric layer 40 comprises formingdielectric layer 40 inside via holes 50, as illustrated in FIG. 3.Dielectric layer 40 must be formed inside via holes 50 so that thesubsequent applying of a first patterned layer of conductive material 60to microelectronic structure 21 does not create an electrically shortedmicroelectronic structure 21.

In one preferred embodiment, dielectric layer 40 is formed by oxidation.During oxidation, a layer of oxide is grown using any one of a number ofprocesses, such as, for example, thermal oxidation, thermal nitridation,anodization, or any other method for growing oxide known to one ofordinary skill in the art. Oxide grown, using any one of the abovementioned processes, forms an insulating film around metal carrier 30and inside via hole 50, as illustrated in FIG. 3.

In one preferred embodiment, dielectric layer 40 is formed by screeninga ceramic paste around metal carrier 30 and inside any via hole 50. Inone preferred embodiment, ceramic paste is screened in such a way as tocreate an insulating layer on the carrier surface, and to coat theinside surface of via holes 50. In one preferred embodiment, the ceramicpaste is then dried in an oven at a temperature of about 25° C. to about150° C., and more preferably about 75° C. In one preferred embodiment,the ceramic paste is then sintered in a furnace at a temperature ofabout 400° C. to about 1800° C., and more preferably about 800° C.

In one preferred embodiment dielectric layer 40 is formed by casting apolymer sheet. In this embodiment, the process for forming dielectriclayer 40 around metal carrier 30 further comprises placing metal carrier30 overlying a first polymer sheet, placing a second polymer sheetoverlying metal carrier 30, and laminating metal carrier 30, the firstpolymer sheet and the second polymer sheet, wherein the first polymersheet fuses to the second polymer sheet. If via holes 50 are formed onmetal carrier 30, then the first polymer sheet fuses to the secondpolymer sheet within via holes 50, and an access hole needs to be formedthrough a portion of the first polymer sheet and the second polymersheet, wherein the access hole is located within via holes 50. Theaccess hole can be formed in any one of the number of ways for forming ahole, such as via holes 50, described above. In one preferredembodiment, dielectric layer 40 is formed by spray or dip coating metalcarrier 30.

Once dielectric layer 40 is formed, a first patterned layer ofconductive material 60 is applied to microelectronic structure 21.Preferably conductive material 60 comprises at least one metal from thegroup consisting of molybdenum, tungsten, silver, palladium, gold,copper, nickel, platinum, and composites such as polymer metal pastes orceramic metal pastes, however, conductive material 60 can comprise anymaterial known to one of ordinary skill in the art, which permits theflow of electrons. Preferably, conductive material 60 comprises the samematerial throughout, however, different materials can be applied tomicroelectronic structure 21 through the fabrication of microelectronicstructure 21. For example, a first patterned layer of conductivematerial 60 may be applied to microelectronic structure 21 usingconductive material 60 which comprises silver, and a second patternedlayer of conductive material 60 may be applied to microelectronicstructure 21 using conductive material 60 which comprises gold.

A patterned layer of conductive material 60 may be applied tomicroelectronic structure 21 in any one of a number of ways known to oneof ordinary skill in the art to form metal wiring, to form groundplanes, to form electrodes 70, to fill via holes 50, or to form anyother metallic structure within microelectronic structure 21, asillustrated in FIG. 1. Conductive material 60 may be applied tomicroelectronic structure 21 in one of a number of ways known to one ofordinary skill in the art, such as, screening a metallic paste, decaltransfer, thin film deposition and electroplating. In one preferredembodiment, a combination of methods such as, screening a metallicpaste, decal transfer, thin film deposition or electroplating, may beused to apply the first patterned layer of conductive material 60 tomicroelectronic structure 21. Multiple patterned layers of conductivematerial 60 may be applied to microelectronic structure 21 by formingdielectric layers 40 overlying the patterned layers of conductivematerial 60, as illustrated in FIG. 1.

In one preferred embodiment, a patterned layer of conductive material 60is applied to microelectronic structure 21 by screening a metallic pastesuch as silverpalladium or copper onto microelectronic structure 21.Once all the layers of the metallic paste have been screened ontomicroelectronic structure 21, microelectronic structure 21 is sinteredat the appropriate temperatures. For example, in one preferredembodiment microelectronic structure 21 is sintered in a furnace at atemperature of about 600° C. to about 1000° C. for about 300 minutes. Inthe case of sintering screened on ceramic pastes and metallic pastes,the use of metal carrier 30 allows one to control the shrinkage ofmicroelectronic structure 21 with extremely high accuracy, thus makingpossible the fabrication of multiple microelectronic structures 21 andthe joining together of multiple; microelectronic structures 21 withhigh tolerances. Even higher tolerances may be obtained when thin filmdielectrics or polymers are used to form dielectrics layer 40, since theforming of dielectric layer 40 using thin film dielectrics or polymersmay be carried out in a protective ambient environment in order toprevent any reaction with metal carrier 30.

In one preferred embodiment, a patterned layer of conductive material 60is applied to microelectronic structure 21 by using an electroplatingprocess. In this preferred embodiment, a seed layer is deposited on allsurfaces of microelectronic structure 21 that are required to bond witha conductive metal. For example, in one preferred embodiment, the seedlayer is deposited using a resist stencil inside via holes 50 and on thesurfaces of the dielectric layer 40. Once the seed layer is deposited,the surface of the seed layer is electroplated using a patterningplating process with a conductive metal, such as silver, palladium,nickel, copper, gold, platinum, or any other material known to one ofordinary skill in the art which permits the flow of electrons. In onepreferred embodiment, the conductive metal in the patterning platingprocess comprises solder, since solder may be used to join onemicroelectronic structure 21 to a semiconductor chip 22 or a secondmicroelectronic structure 21, as illustrated in FIG. 6. While only a fewselect processes for applying a patterned layer of conductive material60 to metal carrier 30 have been described above, any one of a number ofprocesses known to one of ordinary skill in the art may be used.

In one preferred embodiment, once the patterned layers of conductivematerial 60 and the dielectric layers 40 have been applied to metalcarrier 30, an attachment layer of conductive material 60 may be appliedto substrate package 20 in order to facilitate the attachment of onemicroelectronic structure 21, such as first microelectronic structure24, to another microelectronic structure 21, such as secondmicroelectronic structure 26, as illustrated in FIG. 6. In one preferredembodiment before individual microelectronic structures 21 are attachedto one another or to other devices such as semiconductor chip 22,individual microelectronic structures 21, such as first microelectronicstructure 24, are inspected to identify defects. Preferably,microelectronic structures 21 are electronically tested to identify anydefects, and repaired if necessary.

In one preferred embodiment, first microelectronic structure 24 isjoined to second microelectronic structure 26. First microelectronicstructure 24 may be joined to second microelectronic structure 26 usingany one of a number of processes, such as, solder bump technology,lamination, and electrically conducting organic interconnections, asillustrated in FIG. 6.

In one preferred embodiment, multiple microelectronic structures 21 areall fabricated on a single metal carrier 30. In this embodiment, uponfabricating microelectronic structures 21, the single metal carrier 30is diced into multiple microelectronic structures 21. Dicing involvescutting the single metal carrier 30 into multiple metal carriers 30.

The preferred embodiments described above describe only some of the manypossible methods and processes for creating microelectronic structures21. Since there are many possible methods and processes for creatingmicroelectronic structures 21, a description of the physical structuresof microelectronic structure 21 will be necessary.

FIG. 1 illustrates the physical structure for microelectronic structure21, which can be formed by the above-described processes and methods.Microelectronic structure 21 comprises metal carrier 30 having topsurface 32 and bottom surface 34. Metal carrier 30 is processed topromote adhesion, as described above. In one preferred embodiment, metalcarrier 30 comprises via holes 50, formed in accordance with the abovedescribed methods. Via holes 50 comprise an inside surface which definesperimeter of via holes 50. Dielectric layer 40 overlies metal carrier30, substantially covering top surface 32 and bottom surface 34 of metalcarrier 30. In one preferred embodiment, dielectric layer 40substantially covers the inside surface of via holes 50. A firstpatterned layer of conductive material 60 overlies dielectric layer 40.In one preferred embodiment, the first patterned layer of conductivematerial 60 overlies metal carrier 30. Additional patterned layers ofconductive material 60 may placed over metal carrier 30 by placingadditional dielectric layers 40 over existing patterned layers ofconductive material 60, as illustrated in FIG. 1.

In one preferred embodiment, once the patterned layers of conductivematerial 60 and the dielectric layers 40 have been applied to metalcarrier 30, an attachment layer of conductive material 60 may be placedoverlying substrate package 20 in order to facilitate the attachment ofone microelectronic structure 21, such as first microelectronicstructure 24, to another microelectronic structure 21, such as secondmicroelectronic structure 26, as illustrated in FIG. 6.

It is to be understood that a wide range of changes and modifications tothe embodiments described above will be apparent to those skilled in theart are contemplated. It is therefore intended that the foregoingdetailed description be regarded as illustrative, rather than limiting,and that it be understood that it is the following claims, including allequivalents, that are intended to define the spirit and scope of theinvention.

What is claimed is:
 1. A process for fabricating a microelectronicstructure comprising: processing a metal carrier having a top surfaceand a bottom surface; forming a dielectric layer around the metalcarrier, wherein the dielectric layer substantially covers the topsurface and the bottom surface of the metal carrier, and wherein thedielectric layer comprises a material selected from the group consistingof alumina, mullite, aluminum nitride, forsterite, glass, ceramic, andoxide; and applying a first patterned layer of conductive material tothe microelectronic structure.
 2. The process of claim 1, furthercomprising sintering the metal carrier, the dielectric layer, and thefirst patterned layer of conductive material.
 3. The process of claim 1,wherein the processing of the metal carrier comprises a process selectedfrom the group consisting of wet etching, plasma etching, ion milling,and reactive ion etching.
 4. The process of claim 1, further comprisingforming a via hole through the metal carrier before the forming of thedielectric layer around the metal carrier, wherein the forming of thedielectric layer comprises forming the dielectric layer inside the viahole.
 5. The process of claim 4, wherein the forming of the dielectriclayer around the metal carrier comprises screening a ceramic pastearound the metal carrier and inside the via hole.
 6. The process ofclaim 4, wherein the forming of the dielectric layer around the metalcarrier comprises growing an oxide layer.
 7. The process of claim 1,wherein the applying of the first patterned layer of conductive materialto the microelectronic structure comprises a process selected from thegroup consisting of screening, decal transfer, deposition, andelectroplating.
 8. The process of claim 2, further comprising applying asecond patterned layer of conductive material to the microelectronicstructure after the sintering of the metal carrier.
 9. The process ofclaim 8, wherein the applying of the second patterned layer ofconductive material to the microelectronic structure comprises a processselected from the group consisting of screening, decal transfer,deposition, and electroplating.
 10. The process of claim 1, wherein theforming of the dielectric layer around the metal carrier comprisesforming the dielectric layer using a process selected from the groupconsisting of screening a ceramic paste, thin film deposition, andgrowing an oxide layer.
 11. A process for making an electronic devicecomprising: fabricating a first microelectronic structure by the processof claim 10, wherein the first microelectronic structure comprises atleast one electrode extending from the first microelectronic structure;and forming the electronic device comprising the first microelectronicstructure.
 12. The process of claim 11 further comprising inspecting thefirst microelectronic structure to identify defects.
 13. The process ofclaim 11 further comprising: fabricating a second microelectronicstructure by the process of claim 10, wherein the second microelectronicstructure comprises at least one electrode extending from the secondmicroelectronic structure; joining the at least one electrode extendingfrom the first microelectronic structure to the at least one electrodeextending from the second microelectronic structure; and forming theelectronic device comprising the first microelectronic structure and thesecond microelectronic structure.
 14. The process of claim 13, whereinthe joining of the first microelectronic structure to the secondmicroelectronic structure comprises a process selected from the groupconsisting of solder bump technology, lamination, and electricallyconducting organic interconnections.
 15. The process of claim 13,further comprising inspecting the first microelectronic structure andthe second microelectronic structure to identify defects before thejoining of the first microelectronic structure to the secondmicroelectronic structure.
 16. A process for fabricating amicroelectronic structure comprising: applying a first patterned layerof conductive material to a dielectric layer, wherein the dielectriclayer is formed around a metal carrier having a top surface and a bottomsurface, the dielectric layer substantially covering the top surface andthe bottom surface of the metal carrier, and wherein the dielectriclayer comprises a material selected from the group consisting ofalumina, mullite, aluminum nitride, forsterite, glass, ceramic, andoxide.
 17. The process of claim 16, further comprising sintering themetal carrier, the dielectric layer, and the first patterned layer ofconductive material.
 18. The process of claim 16, further comprisingforming a via hole through the metal carrier before the applying of thefirst patterned layer of conductive material to the dielectric layer,wherein the dielectric layer is formed inside the via hole.
 19. Theprocess of claim 1, wherein the top surface and the bottom surface ofthe metal carrier are processed to promote adhesion.
 20. A process forfabricating a microelectronic structure comprising: processing a metalcarrier having a top surface and a bottom surface; forming a dielectriclayer on the top surface of the metal carrier; and applying a firstpatterned layer of conductive material to the microelectronic structure.21. The process of claim 1 further comprising forming a protective layeron all the surfaces of the metal carrier except for the top surface ofthe metal carrier.
 22. The process of claim 20, further comprisingsintering the metal carrier, the dielectric layer, and the firstpatterned layer of conductive material.
 23. The process of claim 20,wherein the processing of the metal carrier comprises a process selectedfrom the group consisting of wet etching, plasma etching, ion milling,and reactive ion etching.
 24. The process of claim 20, furthercomprising forming a via hole in the dielectric layer, whereinconductive material is placed inside the via hole.
 25. The process ofclaim 20, wherein the forming of the dielectric layer on the top surfaceof the metal carrier comprises screening a ceramic paste on the metalcarrier.
 26. The process of claim 20, wherein the forming of thedielectric layer on the metal carrier comprises growing an oxide layer.27. The process of claim 21, wherein the protective layer comprises atleast one material selected from the group consisting of nickel andgold.
 28. The process of claim 21, wherein the protective layersubstantially covers all the surfaces of the metal carrier except forthe top surface of the metal carrier.
 29. The process of claim 20,wherein the applying of the first patterned layer of conductive materialto the microelectronic structure comprises a process selected from thegroup consisting of screening, decal transfer, deposition, andelectroplating.
 30. The process of claim 22, further comprising applyinga second patterned layer of conductive material to the microelectronicstructure after the sintering of the metal carrier.
 31. The process ofclaim 30, wherein the applying of the second patterned layer ofconductive material to the microelectronic structure comprises a processselected from the group consisting of screening, decal transfer,deposition, and electroplating.
 32. The process of claim 20, wherein theforming of the dielectric layer around the metal carrier comprisesforming the dielectric layer using a process selected from the groupconsisting of screening a dielectric paste, casting a polymer sheet,thin film deposition, and growing an oxide.